As is known, thin-film polysilicon transistors have assumed, in the field of low-temperature polysilicon (LTPS) technologies, a fundamental role in a wide range of sectors of consumer micro-electronics (such as, for example, that of active-matrix displays), mainly due to the development of laser crystallization techniques. These techniques, in fact, enable values of mobility of crystallized layers to be obtained higher than 100 cm2/V·s, i.e., more than two orders of magnitude higher than that of TFT devices integrated on amorphous silicon. It has consequently become possible to obtain high levels of electrical performance, comparable with those of traditional MOS devices made on crystalline silicon, at a lower manufacturing cost, and above all with the possibility of application on a non-conventional substrate, such as, for example, a flexible substrate. However, TFT devices still have problems in terms of optimization of structure and process, in particular for applications wherein it is important to associate high densities of integration to low production costs.
A known process for manufacturing self-aligned TFT devices using ion-implantation techniques is described briefly with reference to FIGS. 1-6. For further information, see for example: Min-Cheol Lee, Min-Koo Han, IEEE Electron Device Letters, vol. 25, No. 1, January 2004.
In detail (see FIG. 1), an amorphous silicon layer 2 is initially deposited on a quartz substrate 1 using a PECVD process. Then, a step of dehydrogenation in inert environment is carried out, which enables the hydrogen accumulated in the amorphous silicon layer 2 to flow out in order to prevent any possible phenomena of micro-explosions during subsequent steps of the process. Then, the amorphous silicon layer 2 undergoes a crystallization process through irradiation with an excimer laser XeCl (represented by the arrows in FIG. 1), consequently undergoing a conversion into a polysilicon layer 2.
Next (see FIG. 2), via a reactive ion etching (RIE) of the polysilicon layer 2, active islands 2a of the TFT device are defined, which are designed for integration of the TFT transistors. A gate-oxide layer 3 (made of TEOS—TetraEthylOrthoSilicate) is then deposited using an ECR-PECVD process. The gate-oxide layer 3 acts also as insulator between contiguous active islands 2a. Then, a metallization layer 4, made of an aluminium-silicon-copper alloy, is deposited by sputtering.
Next (FIG. 3), a photolithographic process is carried out for etching of the gate-oxide layer 3 and of the metallization layer 4, which leads to the formation of gate structures 5, constituted by remaining stacked portions 3a and 4a of the aforesaid etched layers.
Through appropriate implantation masks, implantations of dopant of an N+ type and P+ type self-aligned to the gate structures 5 are then performed (FIG. 4) for the formation of source and drain regions of the N-channel TFT devices (the regions being designated, respectively, by the reference numbers 6a, 6b) and of source and drain regions of the P-channel TFT devices (the regions being designated, respectively, by the reference numbers 7a, 7b). In particular, each source region 6a, 7a is separated from a respective drain region 6b, 7b by a channel region 8, which is located underneath a respective gate structure 5. The implanted dopants are then activated via a laser annealing process at an energy density lower than that of the crystallization process.
Then (FIG. 5), an interlayer-oxide layer 9 is deposited using the PECVD technique and is then etched so as to define openings designed for source, drain and gate contacts of the TFT transistors.
Finally (FIG. 6), a metallization layer 10, made of an aluminium-silicon-copper alloy, is deposited and etched for the formation of source (S), drain (D) and gate (G) contacts 11.
This process sequence has some problems and disadvantages. In particular, the laser crystallization step is extremely critical in so far as it contributes to determining the final electrical characteristics of the TFT transistors. In the described process it is, however, difficult to accurately control the growth and size of the grains within the crystallized polysilicon layer. The electron mobility within the crystallized polysilicon layer can also prove insufficient for particular applications. In addition, a single gate metallization is provided for both the N-channel and the P-channel TFT transistors, and it is not possible to adjust the threshold voltage value as a function of the type of conductivity of the channel. In addition, the “cascaded” etching of the metallization layer 4 and of the gate-oxide layer 3 (FIG. 3) is particularly critical in so far as, if not suitably calibrated, it can involve the thin layer of polycrystalline silicon 2 that will define the channel of the TFT devices, thus altering the electrical specifications of the TFT devices.